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555 long time delay circuit 2

2015-02-01 20:38  
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555 long time delay circuit 2
555 long time delay circuit 2
The circuit is shown as the chart 6-2, the delay circuit is a trigger delay circuit with integrator. CA3140 is a BIMOS single-supply op amp, itcan still work when the value ofVref is very low or zero, and its gate (pin 8)can discharge frompin 7of 555 (through D1). Diode D1is required to the J-FET gate - source PN junction with smaller leakage, the conduction current is high, reverse leakage is small (about 100pA). As shown in Figure 5-2, the delay circuit is a trigger delay circuit with integrator. When the negative pulse is triggered, the pin 3 is in high level, and pin 7 is in open circuit, then C2R4 integrator makes line integralon the reference voltage Vref = 0.1V divided by the R1, R2.