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Double-edge detection circuit

2015-01-06 01:54  
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Double-edge detection circuit
Double-edge detection circuit
Figure 1 is the bilateral(rising and falling)detection circuit composed of XOR gate. XOR gate outputs H level when gate input terminal logic is inconsistent, for example, RC circuit easily produces delay time, the edge is detected during rising and falling, then differential pulse is outputed. Figure 2 is the terminal voltage waveform of capacitor C. 74HC86 threshold voltage VTH is VDD / 2, the tag line is released here. From the begining of the corresponding input rising to the time to achieve the C terminal voltage VTH input, the output pulse can be obtained during the time to achieve the C terminal voltage yTH.