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The edge detection circuit using NAND gate

2015-01-03 20:10  
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The edge detection circuit using NAND gate
This circuit is the rising edge detection circuit using the NAND gate previously described, and circuit edge of the output pulse amplitude as T ≈ RC, IC threshold voltage CMOS, T ≈ 0.7RC. In this circuit, when the input is L , the terminal voltage charge of capacitor C is voltage yDD and becomes high level H . When the input is H , before the C terminal voltage reaches y (T = RC), the output level is L . The figure is the input and output waveform of the edge detection circuit. 10pμs negative pulse will be got since the input begins to rise.