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AUDIO LIMITER BERBASIS OP-AMP CIRCUIT SCHEMATIC DIAGRAM

2016-04-17 08:46  
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AUDIO LIMITER BERBASIS OP-AMP CIRCUIT SCHEMATIC DIAGRAM

This audio peak limiter employs a FET as a variable resistance to attenuate the input signal according to a control voltage (CV). It offers unusually good performance with low cost and component count. A TL072 dual opamp (U1) provides the circuit gain and full wave peak detection.


Audio Limiter Berbasis Op-AmpSkema Rangkaian Audio Limiter Berbasis Op-Amp


If desired, a LED VU meter may be used here instead, and with proper calibration will give a good indication of the peak attenuation at any time. This option will require some experimentation from the constructor, and further details are up to the individual to work out.

The 4.7K resistor and 1uF capacitor (R14 and C5) determine the attack time, which is about 5ms as shown. R12 and C5 determine the release or recovery time, and as shown this is approximately 1 second.

R11, C3 C4 and R13 form the distortion cancelling circuit, and as can be seen, the control voltage impedance is very low compared to the distortion cancellation impedance, so the circuit's attack time is not compromised. The values of resistance and capacitance have been optimised for the least distortion across the audio band, at 0.3% THD typical for frequencies above around 500 Hz, at 1.65V RMS output level. Below 500 Hz, the distortion rises gently with decreasing frequency, but also falls with lower voltages. Distortion is negligible at any voltage level below the limiting threshold.