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2016-01-19 15:00  
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The circuit accepts two positive-voltage inputs VN and Vv and provides a TTL-compatible output pulse train whose repetition mte is proportional to the ratio VN/ V0. Full-scale output frequency is about 100 Hz, and linearity error is below 0.5 percent. The outputF, equals KVn/Vd, where K = 1/(4R2C1) provided R1 = R3. Op amp IC1A alternately integrates VN/2 and -VN/2, producing a sawtooth output that ramps between the Vv level and ground. When transistor Ql is on, for example, IC1A integrates -VN/2 until its output equals Vv.

At that time, the IC1B comparator switches low, causing IClD`s bistable output to go low, which turns off Ql. !CIA`s output then ramps in the negative direction. When the output reaches 0 V, the IC1C comparator switches, Ql turns on, and the cycle repeats. Transistor Q2 converts the IC1D output to TTL-compatible output logic levels. Setting Vv to 1.00 V yields a linear voltage-to-frequency converter (F, = KVn), and setting Vn to 1.00 V yields a reciprocal voltage-to-frequency converter (F0=KVd).

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