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74 Series digital circuit of 74LS354/356 8-to-1 data selecto

2016-10-11 14:07  
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74 Series digital circuit of 74LS354/356 8-to-1 data selector(tristate with address latching)
This list shows that the input address is established when the control is low. D1 ~ D7 are the data input. D0n ~ D7n are the steady state input level in D0 ~ D7 line before the latest increasing of the data control or clock pulse. Three-state output with address latching; data register can choose data latch(354) or edge-triggered (356).