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BUFFER_ISUP2_SUPC_DATA_AND_CLOCK_LINES

2016-10-18 19:57  
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BUFFER_ISUP2_SUPC_DATA_AND_CLOCK_LINES
The I2C serial bus is a popular two-wire bus for small-area networks. I2C Clock and Data lines have open collector (or drain) outputs for each device on the network. Only a single pull-up resistor is needed. With this architecture, each device can talk on the network, rather than just listen. In some circumstances, it might be desirable to buffer these lines to expand the network, which can sometimes be a tricky task. The obvious approach (Fig. 1) wont work because it latches in either the higher or lower state. A circuit for a noninventory nonlatching buffer is also shown.The circuit is symmetrical about its center so that the input and output can be swapped. Q1 and Q8 are the output open collector drivers. Q2, Q3, Q6, and Q7 provide the nonlatching functions. The capacitors prevent switching glitches by ensuring the inhibit transistors tum off before the output transistors do.Operation can be best explained by example: if the input is high, Q4 turns off, and the voltage across R8 goes to zero. This tums off Q1 and Q8. The output then goes high, which is the circuit's normal resting place. If the input is pulled Iow, Q4 is tumed on.Diode D1 remains reverse-biased, preventing Q3 from tuming off Q4. With Q4 on, current is sup-plied to both Q2 and Q1 to turn them on, but Q2 turns on first to keep Q1 off. This prevents the in-put from latching. Q4 also turns on Q8. D4 is now forward-biased, so Q6 tums on, and thus tums off Q5. With Q5 off, Q7 will not tum on. The output remains low. Even with both the input and the out-put extemally driven low, the circuit will not latch. The circuit, using the values shown in Fig. 2, reached a clock rate of 80 kHz with a VOH of 5.0 V and a VOL of 0.5 V.