Position: Index > Data Circuit >

Synchronizer PLL data separator circuit

2016-10-18 13:07  
Declaration:We aim to transmit more information by carrying articles . We will delete it soon, if we are involved in the problems of article content ,copyright or other problems.

The function of a data separator is to derive a clock signal from the combined clock/data waveform available from the output of most disk drives. This clock signal should be one suitable for input to one of the popular disk controllers such as the SMC FDC 179X family or the NEC765 controller.The data separator is intended for use with 8` flexible diskettes with IBM 3870 soft sectored format. The circuit delivers data and clock (B) and clock pulses (D). These two signals must be in such a sequence that the negative edge of the clock pulse is at the middle of a data cell. Unseparated data (A) from the floppy unit is shaped with one shot Nl. Trimmer PI should be adjusted so that pulses (B) are 1 ?& wide. This signal synchronizes  PLL  N2 with a free running frequency adjusted to 500 kHz.The output of the PLL is 90?° out of phase with its input. D-type flip-flop N3 is connected as a divider by two and changes state at each positive edge of (C). N4, connected as a shift register, looks for four consecutive missing pulses. When this happens, the circuit is resynchronized with (E) so that the negative edge of (D) is in the middle of a data cell.The disk data separator/synchronizer PLL is subject to aunique set of concerns, all of which can be accommodated when adequate precautions are taken in system design.

Data separator