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2014-11-12 20:40  
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8-digit up/down counter using two cascaded ICM7217 28-pin DIPs. The NAND gate whether a digit is active since one of the two segments not-a or not-b is active on any unblanked number. The flip-flop is clocked by the LSB of the higher-order counter so if this digit is unblanked the Q output of the flip-flop goes high and turns on the NPN transistor, inhibiting leading zero blanking on the lower-order counter (courtesy Intersil, Inc.).