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Logic Signal Long Time Delay Circuit

2014-11-26 18:41  
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Logic Signal Long Time Delay Circuit
If you want to make the serial input logic signal Vtoutputafter thedelay time, it could use the circuit shown in the picture. This circuit uses a RAM and a binary counter. They could both use a same clock signal CP. In the first half cycle of the clock signal, the counter's data would add 1 which would output as the address for reading data. In the next half cycle of the clock signal the new input data Vf would be writen to the same unit. This signal could be read after the time of td=2n+1Tcp. Here Tcp is the cycle time of the clock signal.