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A dual D flip flop inverter circuit

2014-12-14 22:23  
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This flip-flop is sometimes called a transparent latch, because while Enable is high, the data outputs follow the data input. Because the latch holds the data forever while the enable input is low, it can be used to store information, for example, in a computer memory. Lots of latches plus a big decoder equals one computer memory.If two data-type latches are connected as below, the result is an edge-triggered latch:The circuit uses one-half of a dual D flip-flop as an inverter. When the input decreases, the flip-flop resets, and its Q output increases. When the input increases, the reset line is released and Q gets clocked low. The rc delay between applying the input signal to the flip-flop`s reset input and its clock input enables clocking the flip-flop on the input`s positive edge. A74HC74 dual D flip-flop, for example, requires a minimum recovery time of 5 ns after releasing the reset input before strobing its clock input.Therefore, speccing rc at greater than 7.5 ns provides adequate margin. The slight slowing of the clock edge presents no problem, because the clock input`s maximum allowable rise time is a much longer 500 ns. To prevent skewing ofthe output`s symmetry, limit the maximum input frequency to less than 10 MHz.Classical SR  flip-flops require twoNAND gates for active-low inputs or two NOR gates for active-high inputs. The circuit shown uses only two inverters connected in a latch configuration via resistors R1 and R2. This arrangement is useful when a design requires an SR flip-flop, but there are only a few unused inverters, and no NAND or NOR gates are available.