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CLOCK_INPUT_FREQUENCY_DIVIDER

2017-01-08 16:53  
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CLOCK_INPUT_FREQUENCY_DIVIDER
CLOCK_INPUT_FREQUENCY_DIVIDER
CLOCK_INPUT_FREQUENCY_DIVIDER
ICA, R1 through R3, and Q1 form a current source. The current that charges C1 is given by: The input signal drives ICD. Because ICD's positive input (V+) is slightly offset to +0.1 V, its steady-state output will be near + 13 V. This voltage is sent to ICC through D2, setting ICC's output to +13 V. Therefore, point D is cut off by D1, and C1 is charged by the current source. Assuming the initial voltage on C1 is zero, the maximum voltage (I/Cmax) is given by: The right side of the inequality should be the minimum pulse width (either up time or down time) of the input clock. The circuit, when constructed with standard 74F-type parts, operates without any added delay in the exclusive-0R feedback path and with an input frequency of up to 22.5 MHz. The circuit's output signal will have the same duty cycle as the input clock.