DUAL_8051s_EXECUTE_IN_LOCK_STEP

This hardware-software combination deletes clocks from the slave μP until both μPs synchronize. The firmware loop causes each μP to generate a WR signal once per loop. The circuit exclusive-0Rs the two WR signals to produce a miss-compare pulse. The miss-compare pulse latches into the two JK flip-flops via outputs LOCKSTP1 and LOCKSTP2. A high on these signals indicates that the μPs are in lock-step, causing both μPs' programs' execution to exit the firmware loop. If you use discrete components, you'll probably want to use the 0 output of the JK flip-flop and delete the circuit's inverters. The listing uses the μPs' ports 1 and 3. You cannot use a memory-mapped location for the lock-stepdetect clear (K input) because this scheme would generate additional WR signals. You could apply this idea to other μPs, perhaps using their RD signals. This way, generating an RD signal to activate the lock-step-detect clear would not affect the synchronization inputs.