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SYMMETRICAL_DIVIDE_BY_5_CLOCK

2017-01-06 06:45  
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SYMMETRICAL_DIVIDE_BY_5_CLOCK
Uses 74163 counter to generate two phases of 1-MHz clock pulse with 50% duty cycle from 5-MHz system reference. One phase is decode of binary 4 from counter, while other is decode of 1 clocked at midbit time. Both phases are recombined in gate G1 to give 2-MHz clock that toggles FF2 to generate desired 1-MHz output.-L. A.Mann, Divider Circuit Maintains Pulse Symmetry, EDN Magazine, July 1, 1972, p 54-55.