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2016-08-09 21:29  
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The common clock oscillator in Fig. 68-19A has two small problems: It might not, in fact, oscillate if the transition regions of its two gates differ. If it does oscillate, it might sometimes oscillate at a slightly lower frequency than its equation predicts because of the finite gain of the first gate. If the circuit does work, oscillation occurs usually because both gates are in the package and, therefore, have logic thresholds only a few millivolts apart.

The circuit in Fig. 68-19B resolves both problems by adding a resistor and a capacitor. The R2/ C2 network provides hysteresis, thus delaying the onset of gate 1 `s transition until Cl has enough voltage to move gate 1 securely through its transition region. When gate 1 is finally in its transition region, C2 provides positive feedback, thus rapidly moving gate 1 out of its transition region.

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