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168-pin, unbuffered SDRAM DIMM introduction

2017-08-10 22:35  
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This article describes a 168-pin, unbuffered SDRAM DIMM introduction. The circuit  is very simple but effective utility, worth Duokanjibian then master the principles of this principle.

 

DIMM=Dual Inline Memory Module

168 pin DIMM

168 pin DIMM?connector? at the motherboard

Front Side (left side 1-42, right side 43-84)

Back Side (left side 85-126, right side 127-168)
Front, Left
PinNon-Parity72 ECC?80 ECC?Description
1VSSVSSVSSGround
2DQ0DQ0DQ0Data 0
3DQ1DQ1DQ1Data 1
4DQ2DQ2DQ2Data 2
5DQ3DQ3DQ3Data 3
6VDDVDDVDD5 VDC or 3.3 VDC
7DQ4DQ4DQ4Data 4
8DQ5DQ5DQ5Data 5
9DQ6DQ6DQ6Data 6
10DQ7DQ7DQ7Data 7
11DQ8DQ8DQ8Data 8
12VSSVSSVSSGround
13DQ9DQ9DQ9Data 9
14DQ10DQ10DQ10Data 10
15DQ11DQ11DQ11Data 11
16DQ12DQ12DQ12Data 12
17DQ13DQ13DQ13Data 13
18VDDVDDVDD5 VDC or 3.3 VDC
19DQ14DQ14DQ14Data 14
20DQ15DQ15DQ15Data 15
21n/cCB0CB0Parity/Check Bit Input/Output 0
22n/cCB1CB1Parity/Check Bit Input/Output 01
23VSSVSSVSSGround
24n/cn/cCB8Parity/Check Bit Input/Output 8
25n/cn/cCB9Parity/Check Bit Input/Output 9
26VDDVDDVDD5 VDC or 3.3 VDC
27/WE/WE/WERead/Write
28DQMB0DQMB0DQMB0Byte Mask signal 0
29DQMB1DQMB1DQMB1Byte Mask signal 1
30/S0/S0/S0Chip Select 0
31DUDUDUDon't Use
32VSSVSSVSSGround
33A0A0A0Address 0
34A2A2A2Address 2
35A4A4A4Address 4
36A6A6A6Address 6
37A8A8A8Address 8
38A10/APA10/APA10/APAddress 10
39BA1BA1BA1Bank Address 1
40VDDVDDVDD5 VDC or 3.3 VDC
41VDDVDDVDD5 VDC or 3.3 VDC
42CK0CK0CK0Clock signal 0
Front, Right
PinNon-Parity72 ECC?80 ECC?Description
43VSSVSSVSSGround
44DUDUDUDon't Use
45/S2/S2/S2Chip Select 2
46DQMB2DQMB2DQMB2Byte Mask signal 2
47DQMB3DQMB3DQMB3Byte Mask signal 3
48DUDUDUDon't Use
49VDDVDDVDD5 VDC or 3.3 VDC
50n/cn/cCB10Parity/Check Bit Input/Output 10
51n/cn/cCB11Parity/Check Bit Input/Output 11
52n/cCB2CB2Parity/Check Bit Input/Output 2
53n/cCB3CB3Parity/Check Bit Input/Output 3
54VSSVSSVSSGround
55DQ16DQ16DQ16Data 16
56DQ17DQ17DQ17Data 17
57DQ18DQ18DQ18Data 18
58DQ19DQ19DQ19Data 19
59VDDVDDVDD5 VDC or 3.3 VDC
60DQ20DQ20DQ20Data 20
61n/cn/cn/cNot connected
62Vref,NCVref,NCVref,NC 
63CKE1CKE1CKE1Clock Enable Signal 1
64VSSVSSVSSGround
65DQ21DQ21DQ21Data 21
66DQ22DQ22DQ22Data 22
67DQ23DQ23DQ23Data 23
68VSSVSSVSSGround
69DQ24DQ24DQ24Data 24
70DQ25DQ25DQ25Data 25
71DQ26DQ26DQ26Data 26
72DQ27DQ27DQ27Data 27
73VDDVDDVDD5 VDC or 3.3 VDC
74DQ28DQ28DQ28Data 28
75DQ29DQ29DQ29Data 29
76DQ30DQ30DQ30Data 30
77DQ31DQ31DQ31Data 31
78VSSVSSVSSGround
79CK2CK2CK2Clock signal 2
80n/cn/cn/cNot connected
81n/cn/cn/cNot connected
82SDASDASDASerial Data
83SCLSCLSCLSerial Clock
84VDDVDDVDD5 VDC or 3.3 VDC
Back, Left
PinNon-Parity72 ECC?80 ECC?Description
85VSSVSSVSSGround
86DQ32DQ32DQ32Data 32
87DQ33DQ33DQ33Data 33
88DQ34DQ34DQ34Data 34
89DQ35DQ35DQ35Data 35
90VDDVDDVDD5 VDC or 3.3 VDC
91DQ36DQ36DQ36Data 36
92DQ37DQ37DQ37Data 37
93DQ38DQ38DQ38Data 38
94DQ39DQ39DQ39Data 39
95DQ40DQ40DQ40Data 40
96VSSVSSVSSGround
97DQ41DQ41DQ41Data 41
98DQ42DQ42DQ42Data 42
99DQ43DQ43DQ43Data 43
100DQ44DQ44DQ44Data 44
101DQ45DQ45DQ45Data 45
102VDDVDDVDD5 VDC or 3.3 VDC
103DQ46DQ46DQ46Data 46
104DQ47DQ47DQ47Data 47
105n/cCB4CB4Parity/Check Bit Input/Output 4
106n/cCB5CB5Parity/Check Bit Input/Output 5
107VSSVSSVSSGround
108n/cn/cCB12Parity/Check Bit Input/Output 12
109n/cn/cCB13Parity/Check Bit Input/Output 13
110VDDVDDVDD5 VDC or 3.3 VDC
111/CAS/CAS/CASColumn Address Strobe
112DQMB4DQMB4DQMB4Byte Mask signal 4
113DQMB5DQMB5DQMB5Byte Mask signal 5
114/S1/S1/S1Chip Select 1
115/RAS/RAS/RASRow Address Strobe
116VSSVSSVSSGround
117A1A1A1Address 1
118A3A3A3Address 3
119A5A5A5Address 5
120A7A7A7Address 7
121A9A9A9Address 9
122BA0BA0BA0Bank Address 0
123A11A11A11Address 11
124VDDVDDVDD5 VDC or 3.3 VDC
125CK1CK1CK1Clock signal 1
126A12A12A12Address 12
Back, Right
PinNon-Parity72 ECC?80 ECC?Description
127VSSVSSVSSGround
128CKE0CKE0CKE0Clock Enable Signal 0
129/S3/S3/S3Chip Select 3
130DQMB6DQMB6DQMB6Byte Mask signal 6
131DQMB7DQMB7DQMB7Byte Mask signal 7
132A13A13A13Address 13
133VDDVDDVDD5 VDC or 3.3 VDC
134n/cn/cCB14Parity/Check Bit Input/Output 14
135n/cn/cCB15Parity/Check Bit Input/Output 15
136n/cCB6CB6Parity/Check Bit Input/Output 6
137n/cCB7CB7Parity/Check Bit Input/Output 7
138VSSVSSVSSGround
139DQ48DQ48DQ48Data 48
140DQ49DQ49DQ49Data 49
141DQ50DQ50DQ50Data 50
142DQ51DQ51DQ51Data 51
143VDDVDDVDD5 VDC or 3.3 VDC
144DQ52DQ52DQ52Data 52
145n/cn/cn/cNot connected
146Vref,NCVref,NCVref,NC 
147n/cn/cn/cNot connected
148VSSVSSVSSGround
149DQ53DQ53DQ53Data 53
150DQ54DQ54DQ54Data 54
151DQ55DQ55DQ55Data 55
152VSSVSSVSSGround
153DQ56DQ56DQ56Data 56
154DQ57DQ57DQ57Data 57
155DQ58DQ58DQ58Data 58
156DQ59DQ59DQ59Data 59
157VDDVDDVDD5 VDC or 3.3 VDC
158DQ60DQ60DQ60Data 60
159DQ61DQ61DQ61Data 61
160DQ62DQ62DQ62Data 62
161DQ63DQ63DQ63Data 63
162VSSVSSVSSGround
163CK3CK3CK3Clock signal 3
164n/cn/cn/cNot connected
165SA0SA0SA0Serial address 0
166SA1SA1SA1Serial address 1
167SA2SA2SA2Serial address 2
168VDDVDDVDD5 VDC or 3.3 VDC

 


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