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Kick start guide to start working with Programmable Logic De

2017-12-23 19:04  
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Probably everyone knows what are logical IC’s and how to use them in the design. But if design is more complex, electronics enthusiasts more likely are going to choose microcontrollers as they minimizes the count of external components. But problem is that not everything is possible with microcontrollers. They have many disadvantages when fast response to input signals is needed. Microcontrollers execute operations one by one in sequence (conveyor). So output result will occur after some number of clock cycles. One way is to use hard logic IC’s. But when complexity grows a€“ number of IC packages also increases. This way design board becomes tremendous. So where programmable logic devices (PLD) comes to help. CPLD devices have a number of base elements (gates) without strict electrical interconnection. So designer can program these connections to combine any logical combination. Programmable logical devices allow to construct any logical device including counters, triggers and so on. The limit is only number of base elements and connection lines.

So it is better to start with learning tools that allow to construct logical circuits, simplify them and avoid many mistakes. One of them is MAX plus II BASELINE and CPLD from ALTERA. This software allows to design logical circuits visually that later can be flashed to CPLD device. CPLD devices may be based on EPROM, EEPROM and FLASH technology. I think FLASH technology is most attractive for radio hobbyist because it allows to reprogram multiple times without pain.

In this guide is designing and programing process of Altera CPLD EPM3064A described. This devices is quite cheap and affordable for most hobbyists. It has 44 pins on PLCC package. Other features include: JTAG interface, ISP programmability, 1250 programmable gates. Core voltage is 3.3V while I/O may be 5; 3.3 and 2.5V. Maximum clock frequency 224.3MHz. Also it has buss friendly architecture with slew rate control, I/O can be configured as open-drain, power reduction to 50% mode; security bits for protection and more. Device block diagram:


The MAX3064A architecture is based on linking of high performance Logic Array Block (LAB). Each LAB consist of 16 macrocell arrays. Each LAB is linked together via PIA bus. Each Logical Array Block is fed by 36 signals from PIA bus and control signals. More information about chip structure you can read in datasheet.

In order to program these devices there is special adapter used so called ByteBlasterMV.


Adapter allows fast and effective programming of CPLD devices without significant investment. CPLD can be programmed In System. This means that you don’t have to remove chip from circuit. When programming device pins enters high impedance stage in order to protect itself from unintentional conflicts with other board component.

Programming adapter is really easy to build. And it can serve for programming many other devices that support ISP including microcontrollers.

ByteBlasterMV Circuit

Lets move to designing. As we mentioned for designing project we will use MAX PLUS II from Altera. So you can download it from FTP and install. Then get license for MAX PLUS II Software for Students and Universities for version 10.2, 10.1, or 9.23 and press continue to get registration number.

Then enter your hard disk number(You can obtain your hard drive volume serial number by typing dir /p at a DOS or command prompt on your PC ). Then press continue and fill the form. Then save generated license.dat file which will be sent by email in you computer. Then install MAX PLUS II and then setup license by browsing to license.dat Under Options->License Setup menu. Souldn’t be a problem.

MAX PLUS II system has convenient Graphical interface for project input, compilation and flashing. Circuit may be described in AHDL, VHDL, Verilog HDL languages or simply construct circuits graphically. Project file may be graphical, text or signal. Compiler may process following project files:

Graphical (.gdf);

AHDL (.tdf);

Signal (.wdf);

VHDL (.vhd);

Verilog (.v);

OrCAD circuits (.sch);

input files (.edf);

Xilink Netlist (.xnf);

Alptera project (.adf);

digital automaton (.smf);

other auxiliary files.

Lets create simple project. For this create work directory like C:\ALTERA_WORK\ this is where we will save our project files. The Pres File->New and choose Graphic Editor file and press OK. And save project by namingschetchic.gdfand then select Set Project to Current File in Project menu. The press Assign button and select DeviceEPM3064ALC44-4from device familyMAX3000A.


If you leave Auto in devices, then compiler will select device depending on project size.

In library you can find primitive components:

Logical primitives (located inc:\maxplus2\max2lib\prim\) like AND, OR, NOR with various number of pins;

Discrete logic analogs 74 series(located inc:\maxplus2\max2lib\mf\);

Parametric logical functions that allow to create any type and any complexity of logical devices (located inc:\maxplus2\max2lib\mega_lpm\).

Lets create our own directory where we will store personal component library C:\ALTERA_WORK\Altera_Lib and connect this directory to the project in Options->User Libraries and enter path to this directory (c:\altera_work\altera_lib). You can enter symbol to screen in two ways: by pressing left mouse button in work area and selecting Enter Symbol or by selecting Enter Symbol from Symbol menu bar. In the left bar you can find drawing/editing buttons, so you can connect symbols with line. Input and output pins can be selected from element library named input and output(also you can add name to each). If you need to see to a€?0a€? or a€?1a€? select vcc or gnd. If you need to create your own symbol then open new graphical window and draw component circuit and save it toc:\altera_work\altera_libdirectory and add this file to the project.


If there is no errors, you can test this circuit with simulator. For this openWaveform Editorand save file with same name. In the first row on Name press right mouse button and select menu Enter nodes from SNF. In opened window pres List and then in window you can see all inputs and outputs of circuit. Select Both nodes and assign with =>. In editor you can see waveform where you can set value to 0 or 1 or set level change during time flow.


To simulate output selectSimulator. It automatically generates output signal waveform:


If model works OK then we can draw model symbol by selecting File->New->Symbol Editor file. Draw symbol and assign pin by double clicking left mouse button and entering Full Pinstub name. Save file with same name as model.

To give an idea lets go through a three phase counter project with dynamical indication on three 7 segment LED displays.



(Couldn’t get better circuit view, but this should give an idea)

??All components has to be created as described above. Main project looks like this:


0_3r_commutatoris three phase commutator which dynamically switches each 7 segment LED indicator one by one and gives control signal to multiplexers. Multiplexers connects decimal counters0_2b_10d_counterdepending on which indicator is ON. Decimal counters are connected to binary-seven segment decoder0_bcd_7seg.So each component has to be created separately and saved in your library folder.


<Binary-Decimal counter>


<BCD-7 segment decoder>

When models are saved in library you can use them in main project as multiple times.

After all project is set you can simulate over all project with simulator. An see all device working waveforms:



If project seems to be working without errors, you can assign inputs and outputs to real IC pins. You can do this with FloorPlan Editor. And then compile project. After this connect ButeBlasterMV programmer to device board and press Program button in Programmer window. And project will be flashed.

As you can see MAX PLUS II is really good tool for creating complex logical functions in easy way. Graphical editing saves tons of time comparing to writing in any HDL language.

Source: radio-konst.narod.ru

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