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2017-09-05 22:19  
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In this mode, the timer functions as a one shot. The external capacitor is initially held discharged by a transistor internal to the timer. Applying a negative trigger pulse to pin 2 sets the flip-flop, driving the output high, and releasing the short circuit across the external capacitor. The voltage across the capacitor increases with the time constant r ~ RAC to 213 V5, where the comparator resets the flip-flop and discharges the external capacitor. The output is now in the low state.

Circuit triggering takes place when the negative- going trigger pulse reaches 1/3 Vs; the circuit slaYs in the output high state until the set time elapses. The time the output remains in the high state is 1.1 RAC and can be determined by the graph. A negative pulse applied to pin 4 (reset) during the timing cycle will discharge the external capacitor and start the cycle over again beginning on the positive-going edge of the reset pulse. If reset function is not used, pin 4 should be connected to Vs to avoid false resetting.

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