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PIC 16F877

2018-01-31 16:31  
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Architecture and Memory Organization of PIC 16F877

To know more basics about PIC 16F877, click on the link below.



The basic building block of PIC 16F877 is based on Harvard architecture. This microcontroller also has many advanced features as mentioned in the previous post. Here you can see the basic internal architecture and memory organisation of PIC16F877.

Architecture of PIC16F877

The figure below shows the internal architecture of a PIC16F877A chip.

Internal Architecture of PIC16F877A Chip
Internal Architecture of PIC16F877A Chip


The use of each functional block inside this controller has already been explained in the previous post. Now let us look in to the detailed explanation about each sections inside the PIC 16F877.

Memory Organization of PIC16F877

The memory of a PIC 16F877 chip is divided into 3 sections. They are

    Program memoryData memory andData EEPROM

    1. Program memory

    Program memory contains the programs that are written by the user. The program counter (PC) executes these stored commands one by one. Usually PIC16F877 devices have a 13 bit wide program counter that is capable of addressing 8K×14 bit program memory space. This memory is primarily used for storing the programs that are written (burned) to be used by the PIC. These devices also have 8K*14 bits of flash memory that can be electrically erasable /reprogrammed. Each time we write a new program to the controller, we must delete the old one at that time. The figure below shows the program memory map and stack.

    PIC16f877 Program Memory
    PIC16f877 Program Memory


    Program counters (PC) is used to keep the track of the program execution by holding the address of the current instruction. The counter is automatically incremented to the next instruction during the current instruction execution.

    The PIC16F87XA family has an 8-level deep x 13-bit wide hardware stack. The stack space is not a part of either program or data space and the stack pointers are not readable or writable. In the PIC microcontrollers, this is a special block of RAM memory used only for this purpose.

    Each time the main program execution starts at address 0000 – Reset Vector. The address 0004 is “reserved” for the “interrupt service routine” (ISR).

    2. PIC16F87XA Data Memory Organization

    The data memory of PIC16F877 is separated into multiple banks which contain the general purpose registers (GPR) and special function registers (SPR). According to the type of the microcontroller, these banks may vary. The PIC16F877 chip only has four banks (BANK 0, BANK 1, BANK 2, and BANK4). Each bank holds 128 bytes of addressable memory.

    Data Memory Organization
    Data Memory Organization


    The banked arrangement is necessary because there are only 7 bits are available in the instruction word for the addressing of a register, which gives only 128 addresses. The selection of the banks are determined by control bits RP1, RP0 in the STATUS registers Together the RP1, RP0 and the specified 7 bits effectively form a 9 bit address. The first 32 locations of Banks 1 and 2, and the first 16 locations of Banks2 and 3 are reserved for the mapping of the Special Function Registers (SFR’s).


    A bit of RP1 & RP0 of the STATUS register selects the bank access.

    3. Data EEPROM and FLASH

    The data EEPROM and Flash program memory is readable and writable during normal operation (over the full VDD range). This memory is not directly mapped in the register file space. Instead, it is indirectly addressed through the Special Function Registers. There are six SFRs used to read and write this memory:

    ? EECON1

    ? EECON2

    ? EEDATA

    ? EEDATH

    ? EEADR

    ? EEADRH

    The EEPROM data memory allows single-byte read and writes. The Flash program memory allows single-word reads and four-word block writes. Program memory write operations automatically perform an erase-before write on blocks of four words. A byte write in data EEPROM memory automatically erases the location and writes the new data (erase-before-write). The write time is controlled by an on-chip timer. The write/erase voltages are generated by an on-chip charge pump, rated to operate over the voltage range of the device for byte or word operations.

    To know about the Register Memory Organization, and more of PIC 16F877 click on the link below.


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