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Principle of simultaneous multi-spark module SMSM show

2017-08-15 02:20
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Special literary rich multi-spark Eid  circuit . These common facts, the circuit breaker does not control directly Eid, but an oscillator, it will generate a continuous pulse, these pulses will command Eid. This traditional approach to teaching has tw1o main drawbacks: the first one does not exactly match the moment the spark break point, so it has a delay to this improvisation. This is equivalent to an impromptu modify ignition advance, this will result in uneven engine running. In the high speed range, the time betw1een tw1o impulse can become multi-sparking equipment and time betw1een comparable breaker impulse; This will result in unstable operation engine, trepidations and knockings. In order to avoid this trouble, you need more power outages sparking equipment when the engine speed exceeds a certain value. These thoughts, I imagined the device description forwarded. Several computing elements: an internal combustion engine crankshaft speed is given by the following equation:

where :

n = revolution speed of engine crankshaft (rpm)

M = strokes number (2 or 4)

N = number of sparks per second (sparks frequency, in Hz)

B = number of ignition coils

C = cylinder number

For usual four stroke engines, with 4 cylinders and a single ignition coil, the formula becomes :

From where :

In fig.1 is shown an EID equipped with synchronized multi-spark module.

Shaping the role to provide fixed-length blocks impulses (two on each circuit breaker Ms.) open. In this way to eliminate false impulses, vibrations occur due to exposure. See, the shape of the pulse trigger direct Fitr and as a start impulse, multiple spark module. If the engine speed is a speed limit, the module will produce a series of impulses do complement through an OR gate, the generated sparks Eid supplement. When the speed limit is reached (example, 2000 rpm), added impulse to stop at the module output, so nothing to add spark will be generated. Description: This module is used to control the shape of the impulse from the breaker points. Continuous tw1o betw1een impulse time depends rpm engine, the values ??shown in the upper table.

From whole T interval, only in the first half of this will be generated supplementary sparks, after the main spark produced by the breaker points. This is very important, because generating sparks outside of half of the interval, the spinning distributor could apply these sparks to next cylinder, and this could be very harmful for mechanical parts of engine.In fig. 3 is shown the block-diagram of the multi-spark module.At breaker-points opening, the shaping circuit (not shown in drawing) produces a square impulse having 2 mS. This, named BP,is applied to EID by an OR gate and generate the main spark.

In multi-spark module, during 2 mS interval, a sequence timer (a counter with decoded outputs) accomplishes the initialization of circuits (full operations will be detailed later). When impulse BP disappears, the gate P2 is opened and the counter N1 receives impulses with 1 mS period, from clock generator. This 8 bits counter measures, in fact, the duration betw1een tw1o breaker-points impulses. It can count maximum 255 impulses, each having 1 mS (see the table, this correspond to 120 rpm, far below the free running speed !). At next BP impulse, P2 close and the counting stop. The number stored inside N1 is in fact the time length betw1een tw1o BP impulses.

The sequence timer copy the number stored in N1 to N2, after this resets counter N1. When BP becomes low level, N1 restarts the counting. In the same time, the up/down counter N2, starts counting the impulses having 0.5 mS period, which comes via gate P1. It counts down, but with double speed. In this way the counter N2 reach to 0 after T/2 time. The counter N4 and gate P5 makes the impulses for supplementary sparks (2 mS length).

This counter works only if INH signal is at low level. The fip-flop FF1 marks the interval T/2 in which will be generated supplementary sparks. It is reseted when N2 reach 0. The gates P3 and P4 unlock the flio-flop and start supplementary sparks.Also, these gates switch-off the multi-spark function when engine speed limit is reached (in this case, ~ 2000 rpm). How works this ? In the upper table we can see at about 2000 rpm, the time length betw1een tw1o BP impulses is 15 mS.

This means as after a counting cycle, the first 4 bits of counter N1 will be 111 and next 4, 0000. In this case, P3 gate output will be at low level, and the same value for P4 output.The flip-flop FF1 will be not set, and as result, no supplementary sparks. If the speed engine decrease (time length T increase), the last 4 bits of N1 will have at least one 1 and the flip-flop will be set. This allow to appear supplementary sparks until flip-flop will be reseted by borrow impulse of N2.

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