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Programmable Frequency Divider

2017-08-16 02:32  
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This divider uses a variable-length shift register, a type-D flip-flop, and an inverter. The clock feeds the
Programmable Frequency Divider

flip-flop clock input and the output of the shift register feeds the D input of the flip-flop. The FF output is tied back to the reset input of the shift register so that each clock pulse shifts a ` ` into the 4557. N 1 cycles after the reset pulse is removed. The first `1` will propagate through the register output. The `1` is latched into the FF on the clock`s next falling edge and fed back to the 4557 reset pin, which resets the shift register to zero. When a zero is clocked into the flip-flop on the next falling clock edge, the reset is removed, restarting the process. The divide ratio is (N 2), where = the binary number that is programmed into 4557.

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