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Sample and hold circuit II

2017-08-18 18:49  
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This circuit rapidly charges capacitor CST0 to a voltage equal to an input signal. The input signal is then electrically disconnected from the capacitor with the charge still remaining on CSTO. Since CST0 is in the negative feedback loop of the operational amplifier, the output voltage of the amplifier is equal to the voltage across the capacitor. Ideally, the voltage across CST0 should remain constant causing the output of the amplifier to remain constant as well. However, the voltage across CST0 will decay at a rate proportional to the current being injected or taken out of the current summing node of the amplifier.
Sample and hold circuit II

This current can come from four sources: leakage resistance of CST0, leakage current due to the solid state switch SW2, currents due to high resistance paths on the circuit fixture, and most important, bias current of the operational amplifier. If the ICH8500A operational amplifier is employed, this bids current is almost non-existent (less than O.OlpA). Note that the voltages on the source, drain and gate of switch SW2 are zero or near zero when the circuit is in the hold mode. Careful construction will eliminate stray resistance paths and capacitor resistance can be eliminated if a quality capacitor is selected. The net result is a low drift sample and hold circuit. The circuit can double as an integrator. In this application the input voltage is applied to the integrator input terminal. The time constant of the circuit is the product of Rl and Cg

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