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Square-wave-pulse-extractor

2017-08-24 07:37  
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This circuit traps a single positive pulse from a square-wave train. Following the rising edge of an input command, the pulse-out signal emits a replica of one positive pulse of the clock signal simultane ous with the clock signal`s next rising edge. The 0 input command signal sets the Ql output of flip-flop `----IClA.
Square-wave-pulse-extractor

Consequently, the next rising edge of the clock signal sets the Q2 output of IClB, which allows AND gate IC2C to pass the clock signal`s next positive pulse. AND gates IC2A and IC2B prevent the generation of brief output glitches by delaying the clock signal by tv seconds (two propagation delays).



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