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What is worst-case timing analysis

2017-12-23 02:04  
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Probably many of you PC hardware people have faced similar problems when assembling computer from different parts and it seemed to work properly. But under some circumstances system just crashes without any known reason. Even in my practice I had a sound-card that that works well, but time at the time it just crashes and then computer hangs. Of course I can blame drivers or operating system, but there is another probability that there can some timing failures occur.

There are lots of complex production around us that may have a number of undefined failures due to lack of timing worst-case analysis. Failures may occur due to power supply fluctuations, thermal changes or other conditions.

Worst-case analysis encounter all available information of condition variations that can affect performance of components. Worst-case analysis shows if electronic design meets specifications under variable conditions like temperature, voltage or other variables. Only detailed analysis can prove if design will work reliable under all operating conditions.

An it is proved that it is much better to design reliable hardware than fix the problems later. In many ways worst-case analysis may be implemented in various manufacturing phases automatically. By including several simple tests may save lots of money and impact overall quality.

Usually timing analysis starts with standards. The goal is to meet standard timing diagrams as specified, but in reality each component may add a little influence in it and this way overall variation may be significant. Timing analysis usually determines the sequence of events on bus cycles so that we could delimit time available for each of the components to respond to changes. Measured time can be compared to standard time in datasheets, There are several important timings that are critical to a bus oriented interfacing:

Rise-fall time a€“ the time required for a logical signal to change from 20% to 80% of its final level.



  • Propagation delay time a€“ is the time that taken for a change at the input to cause a change at the output. Even wires have some propagation delay. Example below is of NAND logic element. You can see asymmetrical propagation delay that is common to TT logic as sinking current is better then sourcing(open collector).



  • Setup time a€“ is the amount of time a sampled input signal must be valid and stable prior to a clock signal.

    Hold time a€“ is the time amount that sampled signal mus be held valid after clock signal transition occur;



    TPCKQa€“ propagation delay time; TSUa€“ setup time; THa€“ hold time.

  • Tri-state time a€“ this time is also called a a€?dead timea€? that allows to avoid glitches in the bus, where bus is capable to drive multiple devices at the same line. Dead time is time when no devises are driving to make sure there is a safe margin between the times that two devices are enabled.

    Pulse width and Clock frequency. Pulse width and frequency are important for control signals like memory writing or reading. Driving clock signals of microcontrollers usually must have 50% duty cycle:



    Usually clock frequency should not exceed the limits. It should not be too low if specified and to be higher maximum as this may increase instability. Many enthusiasts like to over-clock the hardware to increase performance, but without knowing how in many cases it ends with hardware failure.

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